LM3S3748 Datasheet, PDF (502/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I²C) Interface
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt. A read of this register returns no meaningful data.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x018
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
STOPIC STARTIC DATAIC
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
0
Name
reserved
STOPIC
STARTIC
DATAIC
Type
RO
WO
WO
WO
Reset
0x00
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stop Condition Interrupt Clear
This bit controls the clearing of the raw interrupt for stop condition detect.
When set, it clears the STOPRIS interrupt bit; otherwise, it has no effect
on the STOPRIS bit value.
Start Condition Interrupt Clear
This bit controls the clearing of the raw interrupt for start condition detect.
When set, it clears the STARTRIS interrupt bit; otherwise, it has no effect
on the STARTRIS bit value.
Data Interrupt Clear
This bit controls the clearing of the raw interrupt for data received and
data requested. When set, it clears the DATARIS interrupt bit; otherwise,
it has no effect on the DATARIS bit value.
502
April 08, 2008
Preliminary