LM3S3748 Datasheet, PDF (232/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Micro Direct Memory Access (μDMA)
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding DMA channel. Writing a 1
disables the specified DMA channel.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
CLR[n]
Type
WO
Reset
-
Description
Clear Channel [n] Enable
Set the appropriate bit to disable the corresponding DMA channel.
Note: The controller disables a channel when it completes the DMA
cycle.
Value Description
0 No Effect
Use the DMAENASET register to enable DMA channels.
1 Disable
Disables channel [n].
232
April 08, 2008
Preliminary