LM3S3748 Datasheet, PDF (697/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Parameter No. Parameter Parameter Name
Min Nom Max
Unit
I3^b
t_SRT I2CSCL/I2CSDA rise time (V_IL =0.5 V to V _IH =2.4 V) - - (see note b)
ns
I4^a
t_DH Data hold time
2-
-
system clocks
I5^c
t_SFT I2CSCL/I2CSDA fall time (V_IH =2.4 V to V _IL =0.5 V) - 9
10
ns
I6^a
t_HT Clock High time
24 -
-
system clocks
I7^a
t_DS Data setup time
18 -
-
system clocks
I8^a
t_SCSR Start condition setup time (for repeated start condition 36 -
-
system clocks
only)
I9^a
t_SCS Stop condition setup time
24 -
-
system clocks
a. Values depend on the value programmed into the TPR bit in the I²C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I ²C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 24-2. I²C Timing
I2
I6
I5
I2CSCL
I1
I4
I7
I8 I3
I9
I2CSDA
24.2.6
Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces to the device must be driven to 0 V_DC or powered down with the same external voltage
regulator controlled by HIB.
The external voltage regulators controlled by HIB must have a settling time of 250 μs or less.
Table 24-15. Hibernation Module Characteristics
Parameter No Parameter
Parameter Name
Min Nom Max Unit
H1
t_{HIB_LOW} Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs
H2
t_{HIB_HIGH} Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs
H3
t_{WAKE_ASSERT} /WAKE assertion time
62 - - μs
H4
t_WAKETOHIB /WAKE assert to /HIB desassert
H5
t_{XOSC_SETTLE} XOSC settling time^a
62 - 124 μs
20 - - ms
H6
t_{HIB_REG_WRITE} Time for a write to non-volatile registers in HIB module to complete 92 - - μs
H7
t_{HIB_TO_VDD} HIB deassert to VDD and VDD25 at minimum operational level
- - 250 μs
H8
R_WAKEPU
WAKE internal pull-up resistor
- 200 - kΩ
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
April 08, 2008
697
Preliminary