LM3S3748 Datasheet, PDF (509/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
■ Clears the USBFADDR register.
■ Clears the USBEPIDX register.
■ Flushes all endpoint FIFOs.
■ Clears all control/status registers.
■ Enables all endpoint interrupts.
■ Generates a reset interrupt.
When the application software driving the USB controller receives a reset interrupt, it closes any
open pipes and waits for bus enumeration to begin.
17.2.1.9 Connect/Disconnect
The USB controller connection to the USB bus is controlled by software. The USB PHY can be
switched between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of
the USBPOWER register. When this SOFTCONN bit is set, the PHY is placed in its normal mode
and the USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller
is placed into a state, in which it will not respond to any USB signaling except a USB reset.
When the SOFTCONN bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are
tristated, and the USB controller appears to other devices on the USB bus as if it has been
disconnected. This is the default so the USB controller appears disconnected until the SOFTCONN
bit has been set. The application software can then choose when to set the PHY into its normal
mode. Systems with a lengthy initialization procedure may use this to ensure that initialization is
complete and the system is ready to perform enumeration before connecting to the USB. Once the
SOFTCONN bit has been set, the USB controller can be disconnected by clearing this bit.
Note: The USB controller does not generate an interrupt when the device is connected to the
host. However, an interrupt is generated when the host terminates a session.
17.2.2
Operation as a Host
When the Stellaris^® USB controller is operating in host mode, it can either be used for point-to-point
communications with another USB device or, when attached to a hub, for communication with
multiple devices. Full-speed and low-speed USB devices are supported, both for point-to-point
communication and for operation through a hub. The USB controller automatically carries out the
necessary transaction translation needed to allow a low-speed or full-speed device to be used with
a USB 2.0 hub. Control, bulk, isochronous and interrupt transactions are supported. This section
describes the USB host controller’s actions with regards to transmit endpoints, receive endpoints,
transaction scheduling, entry into and exit from Suspend mode, and reset.
When in host mode, IN transactions are controlled by an endpoint’s receive interface. All IN
transactions use the receive endpoint registers and all OUT endpoints use the transmit endpoint
registers for a given endpoint. As in device mode, the FIFOs for endpoints should take into account
the maximum packet size for an endpoint.
■ Bulk. Bulk endpoints should be sized to be multiples of the maximum packet size (up to 64
bytes). For instance, if maximum packet size is 64 bytes, the FIFO should be configured to a
multiple of 64-byte packets (64, 128, 192, or 256 bytes). This allows for efficient use of double
buffering or packet splitting (described further in the following sections).
April 08, 2008
509
Preliminary