LM3S3748 Datasheet, PDF (6/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
13.2.1 Sample Sequencers ................................................................................................................ 355
13.2.2 Module Control ........................................................................................................................ 356
13.2.3 Hardware Sample Averaging Circuit ......................................................................................... 357
13.2.4 Analog-to-Digital Converter ...................................................................................................... 357
13.2.5 Differential Sampling ............................................................................................................... 357
13.2.6 Internal Temperature Sensor .................................................................................................... 359
13.3 Initialization and Configuration ................................................................................................. 359
13.3.1 Module Initialization ................................................................................................................. 360
13.3.2 Sample Sequencer Configuration ............................................................................................. 360
13.4 Register Map .......................................................................................................................... 360
13.5 Register Descriptions .............................................................................................................. 361
14 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 386
14.1 Block Diagram ........................................................................................................................ 387
14.2 Functional Description ............................................................................................................. 387
14.2.1 Transmit/Receive Logic ........................................................................................................... 387
14.2.2 Baud-Rate Generation ............................................................................................................. 388
14.2.3 Data Transmission .................................................................................................................. 388
14.2.4 Serial IR (SIR) ......................................................................................................................... 389
14.2.5 FIFO Operation ....................................................................................................................... 390
14.2.6 Interrupts ................................................................................................................................ 390
14.2.7 Loopback Operation ................................................................................................................ 391
14.2.8 DMA Operation ....................................................................................................................... 391
14.2.9 IrDA SIR block ........................................................................................................................ 392
14.3 Initialization and Configuration ................................................................................................. 392
14.4 Register Map .......................................................................................................................... 393
14.5 Register Descriptions .............................................................................................................. 394
15 Synchronous Serial Interface (SSI) ................................................................................ 429
15.1 Block Diagram ........................................................................................................................ 429
15.2 Functional Description ............................................................................................................. 430
15.2.1 Bit Rate Generation ................................................................................................................. 430
15.2.2 FIFO Operation ....................................................................................................................... 430
15.2.3 Interrupts ................................................................................................................................ 430
15.2.4 Frame Formats ....................................................................................................................... 431
15.2.5 DMA Operation ....................................................................................................................... 438
15.3 Initialization and Configuration ................................................................................................. 439
15.4 Register Map .......................................................................................................................... 440
15.5 Register Descriptions .............................................................................................................. 441
16 Inter-Integrated Circuit (I²C) Interface ............................................................................ 468
16.1 Block Diagram ........................................................................................................................ 468
16.2 Functional Description ............................................................................................................. 468
16.2.1 I²C Bus Functional Overview .................................................................................................... 469
16.2.2 Available Speed Modes ........................................................................................................... 471
16.2.3 Interrupts ................................................................................................................................ 472
16.2.4 Loopback Operation ................................................................................................................ 473
16.2.5 Command Sequence Flow Charts ............................................................................................ 473
16.3 Initialization and Configuration ................................................................................................. 479
16.4 I²C Register Map ..................................................................................................................... 480
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April 08, 2008
Preliminary