LM3S3748 Datasheet, PDF (514/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
as the controller can automatically split for bulk transactions if the FIFO is larger than the maximum
packet size. The FIFO can also be configured as a double-buffered FIFO so that interrupts occur
at the end of each packet and allow filling the other half of the FIFO.
If operating as a device, the USB device controllers' soft connect should be enabled when the device
is ready to start communications. This indicates to the host controller that the device is ready to
start the enumeration process. If operating as a host controller, the device soft connect should be
disabled and power should be provided to VBUS via the USB0EPEN signal.
17.4
Register Map
Table 17-1 on page 514 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000.
Table 17-1. Univeral Serial Bus (USB) Controller Register Map
Offset Name
Type
Reset
Description
See
page
0x000 USBFADDR
R/W
0x00
USB Device Functional Address
518
0x001 USBPOWER
R/W
0x20
USB Power
519
0x002 USBTXIS
RO
0x0000
USB Transmit Interrupt Status
521
0x004 USBRXIS
RO
0x0000
USB Receive Interrupt Status
522
0x006 USBTXIE
R/W
0x000F
USB Transmit Interrupt Enable
523
0x008 USBRXIE
R/W
0x000E
USB Receive Interrupt Enable
524
0x00A USBIS
RO
0x00
USB General Interrupt Status
525
0x00B USBIE
R/W
0x06
USB Interrupt Enable
527
0x00C USBFRAME
RO
0x0000
USB Frame Value
529
0x00F USBTEST
R/W
0x00
USB Test Mode
531
0x020 USBFIFO0
R/W
0x0000.0000 USB FIFO Endpoint 0
533
0x024 USBFIFO1
R/W
0x0000.0000 USB FIFO Endpoint 1
533
0x028 USBFIFO2
R/W
0x0000.0000 USB FIFO Endpoint 2
533
0x02C USBFIFO3
R/W
0x0000.0000 USB FIFO Endpoint 3
533
0x060 USBDEVCTL
R/W
0x80
USB Device Control
534
0x062 USBTXFIFOSZ
R/W
0x00
USB Transmit Dynamic FIFO Sizing
536
0x063 USBRXFIFOSZ
R/W
0x00
USB Receive Dynamic FIFO Sizing
536
0x064 USBTXFIFOADD
R/W
0x0000
USB Transmit FIFO Start Address
537
0x066 USBRXFIFOADD
R/W
0x0000
USB Receive FIFO Start Address
537
0x07A USBCONTIM
R/W
0x07D USBFSEOF
R/W
0x07E USBLSEOF
R/W
0x080 USBTXFUNCADDR0
R/W
0x5C
0x77
0x72
0x00
USB Connect Timing
538
USB Full-Speed Last Transaction to End of Frame Timing 539
USB Low-Speed Last Transaction to End of Frame
Timing
540
USB Transmit Functional Address Endpoint 0
541
514
April 08, 2008
Preliminary