LM3S3748 Datasheet, PDF (205/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
9.3.3
9.3.3.1
9.3.3.2
The DMA transfer will now take place. If the interrupt is enabled, then the processor will be notified
by interrupt when the transfer is complete. If needed, the status can be checked by reading bit 30
of the DMAENASET register. This bit will be automatically cleared when the transfer is complete.
The status can also be checked by reading the XFERMODE field of the channel control word at offset
0x1E8. This field will automatically be set to 0 at the end of the transfer.
Configuring a Peripheral for Simple Transmit
This example will set up the μDMA controller to transmit a buffer of data to a peripheral. The peripheral
has a transmit FIFO with a trigger level of 4. The example peripheral will use μDMA channel 7.
Configure the Channel Attributes
First, configure the channel attributes:
1. Set bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
Configure the Channel Control Structure
Now the channel control structure must be configured. This example will transfer 64 8-bit bytes from
a memory buffer to the peripheral's transmit FIFO register. This example uses μDMA channel 7,
and the control structure for channel 7 is at offset 0x070 of the channel control table. The channel
control structure for channel 7 is located at the offsets shown in Table 9-9 on page 205.
Table 9-9. Channel Control Structure Offsets for Channel 7
Offset
Description
Control Table Base + 0x070 Channel 7 Source End Pointer
Control Table Base + 0x074 Channel 7 Destination End Pointer
Control Table Base + 0x078 Channel 7 Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Since the peripheral pointer does not change, it simply points to the peripheral's data register.
1. Set the source end pointer at offset 0x070 to the address of the source buffer + 0x3F.
2. Set the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO
register.
The control word at offset 0x078 must be programmed according to Table 9-10 on page 206.
April 08, 2008
205
Preliminary