LM3S3748 Datasheet, PDF (578/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Register 83: USB Request Packet Count in Block Transfer Endpoint 1
(USBRQPKTCOUNT1), offset 0x304
Register 84: USB Request Packet Count in Block Transfer Endpoint 2
(USBRQPKTCOUNT2), offset 0x308
Register 85: USB Request Packet Count in Block Transfer Endpoint 3
(USBRQPKTCOUNT3), offset 0x30C
Host
This 16-bit read/write register is used in Host mode to specify the number of packets that are to be
transferred in a block transfer of one or more bulk packets to receive endpoint n. The core uses the
value recorded in this register to determine the number of requests to issue where the AUTORQ bit
in the USBRXCSRHn register has been set. See “IN Transactions as a Host” on page 510.
Note: Multiple packets combined into a single bulk packet within the FIFO count as one packet.
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1)
Base 0x4005.0000
Offset 0x304
Type R/W, reset 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COUNT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
15:0
Name
COUNT
Type
R/W
Reset
0x00
Description
Block Transfer Packet Count
Sets the number of packets of size MaxP that are to be transferred in
a block transfer.
Note: This is only used in Host mode when AUTORQ is set. The bit
has no effect in Device mode or when AUTORQ is not set.
578
April 08, 2008
Preliminary