LM3S3748 Datasheet, PDF (633/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Bit/Field
7:6
5
4
3
2
1
0
Name
GenAUpd
CmpBUpd
CmpAUpd
LoadUpd
Debug
Mode
Enable
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
Description
PWMnGENA Update Mode
Specifies the update mode for the PWMnGENA register.
Value Description
0 Immediate
The PWMnGENA register value is immediately updated on a
write.
1 Reserved
2 Locally Synchronized
Updates to the register are reflected to the generator the next
time the counter is 0.
3 Globally Synchronized
Updates to the register are delayed until the next time the
counter is 0 after a synchronous update has been requested
through the PWM Master Control (PWMCTL) register.
0
Comparator B Update Mode
Same as CmpAUpd but for the comparator B register.
0
Comparator A Update Mode
The Update mode for the comparator A register. When not set, updates
to the register are reflected to the comparator the next time the counter
is 0. When set, updates to the register are delayed until the next time
the counter is 0 after a synchronous update has been requested through
the PWM Master Control (PWMCTL) register (see page 613).
0
Load Register Update Mode
The Update mode for the load register. When not set, updates to the
register are reflected to the counter the next time the counter is 0. When
set, updates to the register are delayed until the next time the counter
is 0 after a synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
0
Debug Mode
The behavior of the counter in Debug mode. When not set, the counter
stops running when it next reaches 0, and continues running again when
no longer in Debug mode. When set, the counter always runs.
0
Counter Mode
The mode for the counter. When not set, the counter counts down from
the load value to 0 and then wraps back to the load value (Count-Down
mode). When set, the counter counts up from 0 to the load value, back
down to 0, and then repeats (Count-Up/Down mode).
0
PWM Block Enable
Master enable for the PWM generation block. When not set, the entire
block is disabled and not clocked. When set, the block is enabled and
produces PWM signals.
April 08, 2008
633
Preliminary