LM3S3748 Datasheet, PDF (20/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
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USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 .............. 566
USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 .............. 566
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 571
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 571
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 571
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................... 572
USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................... 572
USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................... 572
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ....................... 574
USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ....................... 574
USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ....................... 574
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................... 575
USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................... 575
USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................... 575
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ............. 577
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ............ 577
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ............ 577
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset
0x304 ........................................................................................................................... 578
USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset
0x308 ........................................................................................................................... 578
USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset
0x30C ........................................................................................................................... 578
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 579
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 580
USB External Power Control (USBEPC), offset 0x400 ...................................................... 581
USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ................. 584
USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 ............................ 585
USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ......... 586
USB Device Resume Raw Interrupt Status (USBDRRIS), offset 0x410 .............................. 587
USB Device Resume Interrupt Mask (USBDRIM), offset 0x414 ......................................... 588
USB Device Resume Interrupt Status and Clear (USBDRISC), offset 0x418 ...................... 589
USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................... 590
Analog Comparators ................................................................................................................... 591
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 596
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 597
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 598
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 599
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 600
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 600
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 601
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 601
Pulse Width Modulator (PWM) .................................................................................................... 603
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 613
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 614
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 615
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 617
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 618
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April 08, 2008
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