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LM3S3748 Datasheet, PDF (32/753 Pages) List of Unclassifed Manufacturers – Microcontroller | |||
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Architectural Overview
⢠Synchronization of timers in the PWM generator blocks
⢠Synchronization of timer/comparator updates across the PWM generator blocks
⢠Interrupt status summary of the PWM generator blocks
â Can initiate an ADC sample sequence
â QEI
â Hardware position integrator tracks the encoder position
â Velocity capture using built-in timer
â Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
â GPIOs
â 3-61 GPIOs, depending on configuration
â 5-V-tolerant input/outputs
â Programmable interrupt generation as either edge-triggered or level-sensitive
â Low interrupt latency; as low as 6 cycles and never more than 12 cycles
â Bit masking in both read and write operations through address lines
â Can initiate an ADC sample sequence
â Pins configured as digital inputs are Schmitt-triggered.
â Programmable control for GPIO pad configuration:
⢠Weak pull-up or pull-down resistors
⢠2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
⢠Slew rate control for the 8-mA drive
⢠Open drain enables
⢠Digital input enables
â Power
â On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
â Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
â Low-power options on controller: Sleep and Deep-sleep modes
â Low-power options for peripherals: software controls shutdown of individual peripherals
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April 08, 2008
Preliminary
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