LM3S3748 Datasheet, PDF (472/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I²C) Interface
System Clock Timer Period Standard Mode Timer Period Fast Mode
50Mhz
0x18
100 Kbps
0x06
357 Kbps
16.2.3
Interrupts
The I²C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
■ Stop condition on bus detected
■ Start condition on bus detected
There is a separate interrupt signal for the I²C master and I²C slave modules. While both modules
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
16.2.3.1 I²C Master Interrupts
The I²C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I²C master interrupt, software
must write a '1' to the I²C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I²C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I²C Master Interrupt
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I²C Master Raw Interrupt Status (I2CMRIS) register.
16.2.3.2
I²C Slave Interrupts
The slave module generates interrupts as it receives data and transmit requests from an I²C master.
The slave module also generates interrupts when a start and stop condition is detected. To enable
an I²C slave interrupt, write a '1' to the appropriate bit in the I²C Slave Interrupt Mask (I2CSIMR)
register. Software determines whether the module should write (transmit) or read (receive) data
from the I²C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I²C Slave
Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a
transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a
'1' to the I²C Slave Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I²C Slave Raw Interrupt Status (I2CSRIS) register.
472
April 08, 2008
Preliminary