LM3S3748 Datasheet, PDF (561/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Bit/Field
5
4
3
2
1:0
Name
MODE
DMAEN
FDT
DMAMOD
reserved
Type
R/W
R/W
R/W
R/W
RO
Reset
0
0
0
0
0x00
Description
Mode
The CPU sets this bit to enable the endpoint direction as TX, and clears
the bit to enable it as RX.
Note: This bit only has an effect where the same endpoint FIFO is
used for both transmit and receive transactions.
DMA Request Enable
The CPU sets this bit to enable the DMA request for the transmit
endpoint.
Force Data Toggle
The CPU sets this bit to force the endpoint data toggle to switch and
the data packet to be cleared from the FIFO, regardless of whether an
ACK was received. This can be used by interrupt transmit endpoints
that are used to communicate rate feedback for isochronous endpoints.
DMA Request Mode
The CPU sets this bit to select DMA Request Mode 1 and clears it to
select DMA Request Mode 0.
Note: This bit must not be cleared either before or in the same cycle
as the above DMAEN bit is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
561
Preliminary