LM3S3748 Datasheet, PDF (438/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Synchronous Serial Interface (SSI)
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer)
SSIClk
SSIFss
SSITx
LSB
MSB
SSIRx
0 MSB
LSB
4 to 16 bits
output data
8-bit control
LSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 15-12 on page 438 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
t_Setup=(2*t_SSIClk)
t_Hold=t_SSIClk
SSIClk
SSIFss
15.2.5
SSIRx
First RX data to be
sampled by SSI slave
DMA Operation
The SSI peripheral provides an interface connected to the μDMA controller. The DMA operation of
the SSI is enabled through the SSI DMA Control (SSIDMACTL) register. When DMA operation is
enabled, the SSI will assert a DMA request on the receive or transmit channel when the associated
FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever
there is any data in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is 4 or more items. For the transmit channel, a single transfer request is
asserted whenever there is at least one empty location in the transmit FIFO. The burst request is
asserted whenever the transmit FIFO has 4 or more empty slots. The single and burst DMA transfer
requests are handled automatically by the μDMA controller depending how the DMA channel is
configured. To enable DMA operation for the receive channel, the RXDMAE bit of the DMA Control
(SSIDMACTL) register should be set. To enable DMA operation for the transmit channel, the TXDMAE
bit of SSIDMACTL should be set. If DMA is enabled, then the μDMA controller will trigger an interrupt
when a transfer is complete. The interrupt will occur on the SSI interrupt vector. Therefore, if interrupts
438
April 08, 2008
Preliminary