LM3S3748 Datasheet, PDF (14/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 158
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 159
Internal Memory ........................................................................................................................... 160
Register 1: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 166
Register 2: Flash Memory Address (FMA), offset 0x000 .................................................................... 167
Register 3: Flash Memory Data (FMD), offset 0x004 ......................................................................... 168
Register 4: Flash Memory Control (FMC), offset 0x008 ..................................................................... 169
Register 5: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 171
Register 6: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 172
Register 7: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 173
Register 8: USec Reload (USECRL), offset 0x140 ............................................................................ 174
Register 9: ROM Version Register (RMVER), offset 0x0F4 ................................................................ 175
Register 10: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 176
Register 11: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 177
Register 12: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 178
Register 13: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 179
Register 14: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 180
Register 15: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 181
Register 16: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 182
Register 17: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 183
Register 18: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 184
Register 19: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 185
Register 20: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 186
Register 21: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 187
Register 22: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 188
Micro Direct Memory Access (μDMA) ........................................................................................ 189
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 211
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 212
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 213
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 217
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 219
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 220
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 221
Register 8: DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 ............................. 222
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 223
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 224
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 226
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 227
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 229
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 230
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 232
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 233
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 235
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 236
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 238
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 239
Register 21: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 241
Register 22: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 242
14
April 08, 2008
Preliminary