LM3S3748 Datasheet, PDF (569/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Bit/Field
7
Name
AUTOCL
Type
R/W
6
ISO
R/W
5
DMAEN
R/W
4
DISNYET/PIDERR
R/W
Reset
0
0
0
0
Description
Auto Clear
If the CPU sets this bit, then the RXRDY bit is automatically cleared when
a packet of RXMaxP bytes has been unloaded from the receive FIFO.
When packets of less than the maximum packet size are unloaded,
RXRDY must be cleared manually. When using a DMA to unload the
receive FIFO, data is read from the receive FIFO in 4-byte chunks,
regardless of the RxMaxP. Therefore, the RXRDY bit is cleared as follows:
Remainder (RxMaxP/4)
Value Description
0 RXMaxP = 64 bytes
1 RXMaxP = 61 bytes
2 RXMaxP = 62 bytes
3 RXMaxP = 63 bytes
Actual Bytes Read
Value Description
0 RXMAXP
1 RXMAXP+3
2 RXMAXP+2
3 RXMAXP+1
Packet Sizes that will clear RXPKTRDY.
Value Description
0 RXMAXP, RXMAXP-1, RXMAXP-2, RXMAXP-3
1 RXMAXP
2 RXMAXP, RXMAXP-1
3 RXMAXP, RXMAXP-1, RXMAXP-2
Note: This bit should not be set for high-bandwidth isochronous
endpoints.
ISO
The CPU sets this bit to enable the receive endpoint for isochronous
transfers, and clears it to enable the receive endpoint for bulk/interrupt
transfers.
DMA Request Enable
The CPU sets this bit to enable the DMA request for the receive endpoint.
Disable NYET / PID Error
For bulk or interrupt transactions, the CPU sets this bit to disable the
sending of NYET handshakes. When set, all successfully received
packets are acknowledged, including at the point at which the FIFO
becomes full.
For ISO transactions, the core sets this bit to indicate a PID error in the
received packet.
April 08, 2008
569
Preliminary