LM3S3748 Datasheet, PDF (512/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
An active bulk transaction starts immediately, provided there is sufficient time left in the frame to
complete the transaction before the next SOF packet is due. If the transaction needs to be retried
(for example, because a NAK was received or the target device did not respond), then the transaction
is not retried until the transaction scheduler has first checked all the other endpoints for active
transactions. This ensures that an endpoint that is sending a lot of NAKs does not block other
transactions on the bus. The core also allows the user to specify a limit to the length of time for
NAKs to be received from a target device before the endpoint times out.
17.2.2.5 USB Hubs
The following setup requirements apply to the USB host controller only if it is used with a USB hub.
When a full- or low-speed device is connected to the USB controller via a USB 2.0 hub, details of
the hub address and the hub port also need to be recorded in the corresponding USBRXHUBADDRn
and USBRXHUBPORTn or the USBTXHUBADDRn and USBTXHUBPORTn registers. In addition,
the speed at which the device operates (full or low) needs to be recorded in the USBTYPE0 (endpoint
0), USBTXTYPEn, or USBRXTYPEn registers for each endpoint that is accessed by the device.
For hub communications, the settings in these registers record the current allocation of the endpoints
to the attached USB devices. To maximize the number of devices supported, the USB host controller
allows this allocation to be changed dynamically by simply updating the address and speed
information recorded in these registers. Any changes in the allocation of endpoints to device functions
need to be made following the completion of any on-going transactions on the endpoints affected.
17.2.2.6 Babble
The USB host controller does not start a transaction until the bus has been inactive for at least the
minimum inter-packet delay. It also does not start a transaction unless it can be finished before the
end of the frame. If the bus is still active at the end of a frame, then the USB host controller assumes
that the target device to which it is connected has malfunctioned and the USB controller suspends
all transactions and generates a babble interrupt.
17.2.2.7 Host Suspend
If the SUSPEND bit in the USBPOWER register is set, the USB host controller completes the current
transaction then stops the transaction scheduler and frame counter. No further transactions are
started and no SOF packets are generated.
To exit Suspend mode, the RESUME bit is set and the SUSPEND bit is cleared. While the RESUME bit
is High, the USB host controller generates Resume signaling on the bus. After 20 ms, the RESUME
bit should be cleared, at which point the frame counter and transaction scheduler start. However,
if remote wake-up is to be supported, power to the PHY will be maintained so that the USB controller
can detect Resume signaling on the bus.
17.2.2.8 USB Reset
If the RESET bit in the USBPOWER register is set, the USB host controller generates USB Reset
signaling on the bus. The RESET bit should be set for at least 20 ms to ensure correct resetting of
the target device. After the CPU has cleared the bit, the USB host controller starts its frame counter
and transaction scheduler.
17.2.2.9 Connect/Disconnect
A session is started by setting the SESSION bit in the USBDEVCTL register. This enables the USB
controller to wait for a device to be connected. When a device is detected, a connect interrupt is
generated. The speed of the device that has been connected can be determined by reading the
USBDEVCTL register where the FSDEV bit is High for a full-speed device and the LSDEV bit is High
for a low-speed device. The USB controller should generate a reset to the device and then the USB
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April 08, 2008
Preliminary