LM3S3748 Datasheet, PDF (570/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Bit/Field
3
2:1
0
Name
DMAMOD
reserved
INCRX
Type
R/W
RO
R/W0C
Reset
0
0x00
0
Description
DMA Request Mode
The CPU sets this bit to select DMA Request Mode 1 and clears it to
select DMA Request Mode 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Incomplete Receive
This bit is set in a high-bandwidth isochronous/interrupt transfer if the
packet in the receive FIFO is incomplete because parts of the data were
not received. It is cleared when RXRDY is cleared.
Note: Only valid for isochronous transfers.
570
April 08, 2008
Preliminary