LM3S3748 Datasheet, PDF (13/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
List of Registers
System Control .............................................................................................................................. 66
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 77
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 79
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 80
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 81
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 82
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 83
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 84
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 85
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 90
Register 10: GPIO High Speed Control (GPIOHSCTL), offset 0x06C ..................................................... 91
Register 11: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 93
Register 12: Main Oscillator Control (MOSCCTL), offset 0x07C ............................................................. 95
Register 13: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 96
Register 14: Device Identification 1 (DID1), offset 0x004 ....................................................................... 97
Register 15: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 99
Register 16: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 100
Register 17: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 102
Register 18: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 104
Register 19: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 106
Register 20: Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 107
Register 21: Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 109
Register 22: Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 110
Register 23: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 112
Register 24: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 114
Register 25: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 116
Register 26: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 118
Register 27: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 121
Register 28: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 124
Register 29: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 127
Register 30: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 129
Register 31: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 131
Register 32: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 133
Register 33: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 134
Register 34: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 136
Hibernation Module ..................................................................................................................... 137
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 147
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 148
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 149
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 150
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 151
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 154
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 155
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 156
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 157
April 08, 2008
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Preliminary