LM3S3748 Datasheet, PDF (17/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 380
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 380
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 380
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 380
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 381
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 381
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 382
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 382
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 384
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 385
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 386
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 395
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 397
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 399
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 401
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 402
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 403
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 404
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 406
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 408
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 410
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 412
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 413
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 414
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 416
Register 15: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 417
Register 16: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 418
Register 17: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 419
Register 18: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 420
Register 19: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 421
Register 20: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 422
Register 21: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 423
Register 22: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 424
Register 23: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 425
Register 24: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 426
Register 25: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 427
Register 26: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 428
Synchronous Serial Interface (SSI) ............................................................................................ 429
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 442
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 444
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 446
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 447
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 449
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 450
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 452
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 453
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 454
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 455
April 08, 2008
17
Preliminary