LM3S3748 Datasheet, PDF (255/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
10.1.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
10.2
Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture is
backwards-compatible with previous Stellaris parts and offers two-cycle access time to all GPIO
registers. The high-speed aperture offers the same register map but provides single-cycle access
times. These apertures are mutually exclusive. The aperture enabled for a given GPIO port is
controlled by the appropriate bit in the GPIOHSCTL register (see page 91).
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the four JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 10-1 on page 255
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 10-2 on page 256 shows how a rising edge interrupt would be configured for
pin 2 of a GPIO port.
Table 10-1. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL
Digital Input (GPIO)
0
DIR
0
ODR
0
DEN
1
Digital Output (GPIO)
0
1
0
1
Open Drain Input
0
0
1
1
(GPIO)
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
Digital Input (QEI)
1
X
0
1
Digital Output (PWM)
1
X
0
1
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
Digital Input/Output
1
X
0
1
(UART)
Analog Input
(Comparator)
0
0
0
0
Digital Output
(Comparator)
1
X
0
1
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
PUR
?
?
X
X
X
?
?
?
?
?
?
0
?
PDR
?
?
X
X
X
?
?
?
?
?
?
0
?
DR2R
X
?
X
?
?
X
X
?
?
?
?
X
?
DR4R
X
?
X
?
?
X
X
?
?
?
?
X
?
DR8R
X
?
X
?
?
X
X
?
?
?
?
X
?
SLR
X
?
X
?
?
X
X
?
?
?
?
X
?
April 08, 2008
255
Preliminary