LM3S3748 Datasheet, PDF (531/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Host
Device
Register 11: USB Test Mode (USBTEST), offset 0x00F
USBTESTMODE is an 8-bit register that is primarily used to put the USB controller into one of the
four test modes for operation described in the USB 2.0 specification, in response to a SET FEATURE:
USBTESTMODE command. It is not used in normal operation.
Note: Only one of these bits should be set at any time.
USBTEST Host Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
FORCEH FIFOACC FORCEFS
reserved
Type R/W R/W1S R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
4:0
Name
FORCEH
FIFOACC
FORCEFS
reserved
Type
R/W
R/W1S
R/W
RO
Reset
0
0
0
0x00
Description
Force Host Mode
The CPU sets this bit to instruct the core to enter Host mode when the
Session bit is set, regardless of whether it is connected to any peripheral.
The state of the USBD+ and USBD- are ignored. The core then remains
in Host mode until the SESSION bit is cleared, even if a device is
disconnected, and if the FORCEH bit remains set, re-enters Host mode
the next time the SESSION bit is set.
While in this mode, status of the bus connection may be read from the
DEV bit of the USBDEVCTL register. The operating speed is determined
from the FORCEFS bit.
FIFO Access
The CPU sets this bit to transfer the packet in the endpoint 0 transmit
FIFO to the endpoint 0 receive FIFO. It is cleared automatically.
Force Full-Speed Mode
The CPU sets this bit to force the USB controller into Full-Speed mode
when it receives a USB reset. When 0, the USB controller operates at
Low Speed.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USBTEST Device Mode
USB Test Mode (USBTEST)
Base 0x4005.0000
Offset 0x00F
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
reserved FIFOACC FORCEFS
reserved
Type RO R/W1S R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
April 08, 2008
531
Preliminary