LM3S3748 Datasheet, PDF (507/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
packet is unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than
the maximum, RXRDY must be cleared manually. If the FULL bit was set when RXRDY is cleared,
the USB controller first clears the FULL bit. It then sets RXRDY again to indicate that there is another
packet waiting in the FIFO to be unloaded.
Note: Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the
USBRXDPKTBUFDIS register. This bit is set by default, so it must be cleared to enable
double-packet buffering.
Special Bulk Handling
The packets transferred in bulk operations are defined by the USB specification to be 8, 16, 32, or
64 bytes in size. For some system designs, however, it may be more convenient for the application
software to read larger amounts of data from an endpoint in a single operation than can be transferred
in a single USB operation.
To simplify this case, the Stellaris^® USB controller includes a packet-combining feature that combines
the packets received across the USB bus into larger data packets prior to being read by the
application software. With this option, the USBRXMAXPn register uses the bottom 11 bits to define
the payload for each individual transfer, while the top 5 bits define a multiplier. The USB controller
then combines the appropriate number of USB packets it receives into a single data packet of size
multiplier × payload within the FIFO before asserting RXRDY to alert the application software that a
packet in the FIFO is ready to be read. The size of the resulting packet is reported in the
USBRXCOUNTn register. From the application software’s point-of-view, the resulting operation
does not differ from the receipt of a single USB packet except in the size of the packet read.
Note:
Packet-combining can only be used with bulk endpoints. The payload recorded in the
USBRXMAXPn register must also match the wMaxPacketSize field of the Standard
Endpoint Descriptor for the endpoint (see chapter 9 of the USB specification). The associated
FIFO must also be large enough to accommodate the combined data packet.
The RXRDY bit is only set when either the specified number of packets have been received or a
“short” USB packet is received (that is, a packet of less than the specified payload for the endpoint).
If a protocol is being used in which the endpoint receives bulk transfers that are a multiple of the
recorded payload size with no short packet to terminate it, the USBRXMAXPn register should not
be programmed to expect more packets than there are in the transfer (otherwise, the software will
not be interrupted at the end of the transfer).
17.2.1.4 Scheduling
The device has no control over the scheduling of transactions as this is determined by the host
controller. The Stellaris^® USB controller can set up a transaction at any time. The USB controller
will wait for the request from the host controller and generate an interrupt when the transaction is
complete or if it was terminated due to some error. If the host controller makes a request and the
device controller is not ready, the USB controller sends a busy response (NAK) to all requests until
it is ready.
17.2.1.5 Additional Actions
The USB controller responds automatically to certain conditions on the USB bus or actions by the
host controller: when the USB controller automatically stalls a control transfer and unexpected zero
length OUT data packets.
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
April 08, 2008
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Preliminary