LM3S3748 Datasheet, PDF (440/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Synchronous Serial Interface (SSI)
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
15.4
Register Map
Table 15-1 on page 440 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 15-1. SSI Register Map
Offset Name
Type
0x000 SSICR0
0x004 SSICR1
0x008 SSIDR
0x00C SSISR
0x010 SSICPSR
0x014 SSIIM
0x018 SSIRIS
0x01C SSIMIS
0x020 SSIICR
0x024 SSIDMACTL
0xFD0 SSIPeriphID4
0xFD4 SSIPeriphID5
0xFD8 SSIPeriphID6
0xFDC SSIPeriphID7
0xFE0 SSIPeriphID0
0xFE4 SSIPeriphID1
0xFE8 SSIPeriphID2
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
W1C
R/W
RO
RO
RO
RO
RO
RO
RO
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0003
0x0000.0000
0x0000.0000
0x0000.0008
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0022
0x0000.0000
0x0000.0018
Description
SSI Control 0
SSI Control 1
SSI Data
SSI Status
SSI Clock Prescale
SSI Interrupt Mask
SSI Raw Interrupt Status
SSI Masked Interrupt Status
SSI Interrupt Clear
SSI DMA Control
SSI Peripheral Identification 4
SSI Peripheral Identification 5
SSI Peripheral Identification 6
SSI Peripheral Identification 7
SSI Peripheral Identification 0
SSI Peripheral Identification 1
SSI Peripheral Identification 2
See
page
442
444
446
447
449
450
452
453
454
455
456
457
458
459
460
461
462
440
April 08, 2008
Preliminary