LM3S3748 Datasheet, PDF (556/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Register 53: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1),
offset 0x112
Register 54: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2),
offset 0x122
Register 55: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3),
offset 0x132
Host
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected transmit endpoint.
Device
USBTXCSRL1 Host Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
NAKTO / _{CLRDT STALLED SETUP FLUSH ERROR FIFONE TXRDY}
INCTX
Type R/W0C W1S R/W0C R/W
Reset
0
0
0
0
W1C
0
R/W0C R/W0C R/W0C
0
0
0
Bit/Field
7
6
5
4
Name
NAKTO / INCTX
CLRDT
STALLED
SETUP
Type
R/W0C
W1S
R/W0C
R/W
Reset
0
0
0
0
Description
NAK Timeout / Incomplete TX
Bulk endpoints only: This bit is set when the transmit endpoint is halted
following the receipt of NAK responses for longer than the time set as
the NAK Limit by the USBTXINTERVALn register. The CPU should
clear this bit to allow the endpoint to continue.
High-bandwidth interrupt endpoints only: This bit is set if no response
is received from the device to which the packet is being sent.
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
Endpoint Stalled
This bit is set when a STALL handshake is received. When this bit is
set, any DMA request that is in progress is stopped, the FIFO is
completely flushed, and the TXRDY bit is cleared. The CPU should clear
this bit.
Setup Packet
The CPU sets this bit, at the same time as the TXRDY bit is set, to send
a SETUP token instead of an OUT token for the transaction.
Note: Setting this bit also clears DT.
556
April 08, 2008
Preliminary