LM3S3748 Datasheet, PDF (69/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
6.1.3
6.1.3.1
6.1.3.2
6.1.4
6.1.5
6.1.5.1
The watchdog reset timing is shown in Figure 24-13 on page 702.
Non-Maskable Interrupt
The controller has two sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal.
■ A main oscillator verification error.
If both sources of NMI are enabled, software must check that the main oscillator verification is the
cause of the interrupt in order to distinguish between the two sources.
NMI Pin
The alternate function to GPIO port pin B7 is an NMI signal. The alternate function must be enabled
in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs
(GPIOs)” on page 250. Note that enabling the NMI alternate function requires the use of the GPIO
lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality. The
active sense of the NMI signal is High; asserting the enabled NMI signal above V_IH initiates the NMI
interrupt sequence.
Main Oscillator Verification Failure
The main oscillator verification circuit may generate a reset event and then, during the subsequent
POR, control is transferred to the NMI handler. The detection circuit is enabled using the CVAL bit
in the Main Oscillator Control (MOSCCTL) register. The main oscillator verification error is indicated
in the main oscillator fail status bit (MOSCFAIL bit in the Reset Cause (RESC) register. The main
oscillator verification circuit action is described in more detail in “Clock Control” on page 69.
Power Control
The Stellaris^® microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note:
The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
Clock Control
System control determines the control of clocks in this part.
Fundamental Clock Sources
There are four clock sources for use in the device:
■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
April 08, 2008
69
Preliminary