LM3S3748 Datasheet, PDF (629/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 11: PWM0 Control (PWM0CTL), offset 0x040
Register 12: PWM1 Control (PWM1CTL), offset 0x080
Register 13: PWM2 Control (PWM2CTL), offset 0x0C0
Register 14: PWM3 Control (PWM3CTL), offset 0x100
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and
PWM3 outputs, the PWM2 block produces the PWM4 and PWM5 outputs, and the PWM3 block produces
the PWM6 and PWM7 outputs.
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
31
30
29
28
Type RO
RO
Reset
0
0
Type
Reset
15
14
DBFallUpd
R/W
R/W
0
0
RO
RO
0
0
13
12
DBRiseUpd
R/W
R/W
0
0
27
26
25
24
reserved
RO
RO
RO
RO
0
0
0
0
11
10
DBCtlUpd
R/W
R/W
0
0
9
8
GenBUpd
R/W
R/W
0
0
23
22
21
20
19
18
17
16
LATCH MINFLTPER FLTSRC
RO
RO
RO
RO
RO
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
GenAUpd
CmpBUpd CmpAUpd LoadUpd Debug
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
Mode
R/W
0
0
Enable
R/W
0
Bit/Field
31:19
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
April 08, 2008
629
Preliminary