LM3S3748 Datasheet, PDF (559/753 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S3748 Microcontroller
Register 56: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1),
offset 0x113
Register 57: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2),
offset 0x123
Register 58: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3),
offset 0x133
Host
USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently
selected transmit endpoint.
Device
USBTXCSRHn Host Mode
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1)
Base 0x4005.0000
Offset 0x113
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
AUTOSET reserved MODE DMAEN FDT DMAMOD DTWE
DT
Type R/W
RO
R/W
R/W
R/W
R/W
W1S
R/W
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
4
Name
AUTOSET
reserved
MODE
DMAEN
Type
R/W
RO
R/W
R/W
Reset
0
0
0
0
Description
Auto Set
If the CPU sets this bit, TXRDY is automatically set when data of the
maximum packet size (value in USBTXMAXPn) is loaded into the
transmit FIFO. If a packet of less than the maximum packet size is
loaded, then TXRDY must be set manually.
Note: This bit should not be set for either high-bandwidth
isochronous or high-bandwidth interrupt endpoints.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mode
The CPU sets this bit to enable the endpoint direction as TX, and clears
it to enable the endpoint direction as RX.
Note: This bit only has an effect when the same endpoint FIFO is
used for both transmit and receive transactions.
DMA Request Enable
The CPU sets this bit to enable the DMA request for the transmit
endpoint.
April 08, 2008
559
Preliminary