LM3S3748 Datasheet, PDF (548/753 Pages) List of Unclassifed Manufacturers – Microcontroller

Univeral Serial Bus (USB) Controller
Register 48: USB Control and Status Endpoint 0 Low (USBCSRL0), offset
0x102
Host
USBCSRL0 is an 8-bit register that provides control and status bits for endpoint 0.
Device
USBCSRL0 Host Mode
USB Control and Status Endpoint 0 Low (USBCSRL0)
Base 0x4005.0000
Offset 0x102
Type W1C, reset 0x00
7
6
5
4
3
2
1
0
NAKTO STATUS REQPKT ERROR SETUP STALLED TXRDY RXRDY
Type R/W0C R/W
Reset
0
0
R/W R/W0C R/W1S R/W0C R/W1S R/W0C
0
0
0
0
0
0
Bit/Field
7
6
5
4
3
2
Name
NAKTO
STATUS
REQPKT
ERROR
SETUP
STALLED
Type
R/W0C
R/W
R/W
R/W0C
R/W1S
R/W0C
Reset
0
0
0
0
0
0
Description
NAK Timeout
This bit is set by the USB controller when endpoint 0 is halted following
the receipt of NAK responses for longer than the time set by the
USBNAKLMT register. The CPU should clear this bit by writing a 0 to
it to allow the endpoint to continue.
Status Packet
The CPU sets this bit at the same time as the TXRDY or REQPKT bit is
set, to perform a status stage transaction. Setting this bit ensures DT is
set to 1 so that a DATA1 packet is used for the Status Stage transaction.
Request Packet
The CPU sets this bit to request an IN transaction. It is cleared when
RXRDY is set.
Error
This bit is set by the USB controller when three attempts have been
made to perform a transaction with no response from the peripheral.
The CPU should clear this bit. An interrupt is generated when this bit is
set.
Setup Packet
The CPU sets this bit, at the same time as the TXRDY bit is set, to send
a SETUP token instead of an OUT token for the transaction. This always
resets the data toggle and sends a DATA0 packet.
Endpoint Stalled
This bit is set when a STALL handshake is received. The CPU should
clear this bit.
548
April 08, 2008
Preliminary