DS031 Datasheet, PDF (98/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Pinout Information
Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
Pin Number
2
IO_L96N_2
G11
2
IO_L96P_2
G13
No Connect in the XC2V40
3
IO_L96N_3
G12
3
IO_L96P_3
H12
3
IO_L94N_3
H11
3
IO_L94P_3
J13
3
IO_L03N_3/VREF_3
J10
3
IO_L03P_3
K13
3
IO_L02N_3/VRP_3
K12
3
IO_L02P_3/VRN_3
K11
3
IO_L01N_3
K10
3
IO_L01P_3
L13
4
IO_L01N_4/BUSY/DOUT ⁽¹⁾
M11
4
IO_L01P_4/INIT_B
N11
4
IO_L02N_4/D0/DIN⁽¹⁾
L10
4
IO_L02P_4/D1
M10
4
IO_L03N_4/D2/ALT_VRP_4
N10
4
IO_L03P_4/D3/ALT_VRN_4
K9
4
IO_L94N_4/VREF_4
N9
4
IO_L94P_4
K8
4
IO_L95N_4/GCLK3S
L8
4
IO_L95P_4/GCLK2P
M8
4
IO_L96N_4/GCLK1S
N8
4
IO_L96P_4/GCLK0P
K7
5
IO_L96N_5/GCLK7S
N7
5
IO_L96P_5/GCLK6P
M7
5
IO_L95N_5/GCLK5S
N6
5
IO_L95P_5/GCLK4P
M6
5
IO_L94N_5
L6
5
IO_L94P_5/VREF_5
K6
5
IO_L03N_5/D4/ALT_VRP_5
L5
5
IO_L03P_5/D5/ALT_VRN_5
K5
5
IO_L02N_5/D6
N4
5
IO_L02P_5/D7
M4
5
IO_L01N_5/RDWR_B
L4
5
IO_L01P_5/CS_B
K4
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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