DS031 Datasheet, PDF (73/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 27: Enhanced Pipelined Multiplier Switching Characteristics
Description
Setup and Hold Times Before/After Clock
Data Inputs
Clock Enable
Reset
Clock to Output Pin
Clock to Pin 35
Clock to Pin 34
Clock to Pin 33
Clock to Pin 32
Clock to Pin 31
Clock to Pin 30
Clock to Pin 29
Clock to Pin 28
Clock to Pin 27
Clock to Pin 26
Clock to Pin 25
Clock to Pin 24
Clock to Pin 23
Clock to Pin 22
Clock to Pin 21
Clock to Pin 20
Clock to Pin 19
Clock to Pin 18
Clock to Pin 17
Clock to Pin 16
Clock to Pin 15
Clock to Pin 14
Clock to Pin 13
Clock to Pin 12
Clock to Pin 11
Clock to Pin 10
Clock to Pin 9
Clock to Pin 8
Clock to Pin 7
Clock to Pin 6
Clock to Pin 5
Clock to Pin 4
Clock to Pin 3
Clock to Pin 2
Clock to Pin 1
Clock to Pin 0
Symbol
T_MULIDCK/T_MULCKID
T_{MULIDCK_CE}/T_{MULCKID_CE}
T_{MULIDCK_RST}/T_{MULCKID_RST}
T_{MULTCK1_P35}
T_{MULTCK1_P34}
T_{MULTCK1_P33}
T_{MULTCK1_P32}
T_{MULTCK1_P31}
T_{MULTCK1_P30}
T_{MULTCK1_P29}
T_{MULTCK1_P28}
T_{MULTCK1_P27}
T_{MULTCK1_P26}
T_{MULTCK1_P25}
T_{MULTCK1_P24}
T_{MULTCK1_P23}
T_{MULTCK1_P22}
T_{MULTCK1_P21}
T_{MULTCK1_P20}
T_{MULTCK1_P19}
T_{MULTCK1_P18}
T_{MULTCK1_P17}
T_{MULTCK1_P16}
T_{MULTCK1_P15}
T_{MULTCK1_P14}
T_{MULTCK1_P13}
T_{MULTCK1_P12}
T_{MULTCK1_P11}
T_{MULTCK1_P10}
T_{MULTCK1_P9}
T_{MULTCK1_P8}
T_{MULTCK1_P7}
T_{MULTCK1_P6}
T_{MULTCK1_P5}
T_{MULTCK1_P4}
T_{MULTCK1_P3}
T_{MULTCK1_P2}
T_{MULTCK1_P1}
T_{MULTCK1_P0}
Speed Grade
-6
-5
-4
Units
3.00/0.00
0.72/0.00
0.72/0.00
3.45/0.00
0.80/0.00
0.80/0.00
3.89/0.00
0.86/0.00
0.86/0.00
ns, Max
ns, Max
ns, Max
3.05
3.25
3.74
ns, Max
2.95
3.14
3.61
ns, Max
2.85
3.04
3.49
ns, Max
2.76
2.93
3.37
ns, Max
2.66
2.82
3.25
ns, Max
2.56
2.72
3.12
ns, Max
2.47
2.61
3.00
ns, Max
2.37
2.50
2.88
ns, Max
2.27
2.40
2.75
ns, Max
2.17
2.29
2.63
ns, Max
2.08
2.18
2.51
ns, Max
1.98
2.07
2.38
ns, Max
1.88
1.97
2.26
ns, Max
1.79
1.86
2.14
ns, Max
1.69
1.75
2.02
ns, Max
1.59
1.65
1.89
ns, Max
1.50
1.54
1.77
ns, Max
1.40
1.43
1.65
ns, Max
1.30
1.33
1.52
ns, Max
1.20
1.22
1.40
ns, Max
1.11
1.11
1.28
ns, Max
1.01
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
0.91
1.00
1.15
ns, Max
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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