DS031 Datasheet, PDF (93/318 Pages) Xilinx, Inc – Summary of Features

2
R2
Virtex-II Platform FPGAs:
6
Pinout Information
DS031-4 (v3.5) November 5, 2007
Product Specification
This document provides Virtex-II™ Device/Package Combi-
nations, Maximum I/Os Available, and Virtex-II Pin Defini-
tions, followed by pinout tables for the following packages:
• CS144/CSG144 Chip-Scale BGA Package
• FG256/FGG256 Fine-Pitch BGA Package
• FG456/FGG456 Fine-Pitch BGA Package
• FG676/FGG676 Fine-Pitch BGA Package
• BG575/BGG575 Standard BGA Package
• BG728/BGG728 Standard BGA Package
• FF896 Flip-Chip Fine-Pitch BGA Package
• FF1152 Flip-Chip Fine-Pitch BGA Package
• FF1517 Flip-Chip Fine-Pitch BGA Package
• BF957 Flip-Chip BGA Package
For device pinout diagrams and layout guidelines, refer to
the Virtex-II Platform FPGA User Guide. ASCII package
pinout files are also available for download from the Xilinx
website (www.xilinx.com).
Virtex-II Device/Package Combinations and Maximum I/Os Available
Wire-bond and flip-chip packages are available. Table 1 and
Table 2 show the maximum number of user I/Os possible in
wire-bond and flip-chip packages, respectively.
Table 3 shows the number of user I/Os available for all
device/package combinations.
• CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
• CSG denotes Pb-free wire-bond chip-scale ball grid
array (BGA) (0.80 mm pitch).
• FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
• FGG denotes Pb-free wire-bond fine-pitch BGA (1.00
mm pitch).
• BG denotes standard BGA (1.27 mm pitch).
• BGG denotes Pb-free standard BGA (1.27 mm pitch).
• FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
• BF denotes flip-chip BGA (1.27 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD).
Table 1: Wire-Bond Packages Information
Package ⁽¹⁾
CS144/
CSG144
FG256/
FGG256
FG456/
FGG456
FG676/
FGG676
BG575/
BGG575
Pitch (mm)
0.80
1.00
1.00
1.00
1.27
Size (mm)
12 x 12
17 x 17
23 x 23
27 x 27
31 x 31
I/Os
92
172
324
484
408
Notes:
1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Ordering Examples (Module 1).
BG728/
BGG728
1.27
35 x 35
516
Table 2: Flip-Chip Packages Information
Package
FF896
Pitch (mm)
1.00
Size (mm)
31 x 31
I/Os
624
FF1152
1.00
35 x 35
824
FF1517
1.00
40 x 40
1,108
BF957
1.27
40 x 40
684
© 2000–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
1