DS031 Datasheet, PDF (35/318 Pages) Xilinx, Inc – Summary of Features

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Multiplier Blocks
Virtex-II Platform FPGAs: Functional Description
Multiplier Blocks
Multiplier Blocks
Figure 37: Multipliers (2-column, 4-column, and 6-column)
DS031_39_101000
Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in Figure 38.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in Digital Clock
Manager (DCM), page 29. Each global clock buffer can also
be driven by local interconnects. The DCM has clock out-
put(s) that can be connected to global clock buffer inputs, as
shown in Figure 39.
8 clock pads
Virtex-II
Device
8 clock pads
DS031_42_022305
Figure 38: Virtex-II Clock Pads
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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