DS031 Datasheet, PDF (28/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
3-State Buffers
Introduction
Each Virtex-II CLB contains two 3-state drivers (TBUFs)
that can drive on-chip busses. Each 3-state buffer has its
own 3-state control pin and its own input pin.
Each of the four slices have access to the two 3-state buff-
ers through the switch matrix, as shown in Figure 27.
TBUFs in neighboring CLBs can access slice outputs by
direct connects. The outputs of the 3-state buffers drive hor-
izontal routing resources used to implement 3-state busses.
TBUF
Switch
Matrix
TBUF
Slice
S1
Slice
S3
Slice
S2
Slice
S0
DS031_37_060700
Figure 27: Virtex-II 3-State Buffers
The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predict-
able and less load dependant especially with larger devices.
Locations / Organization
Four horizontal routing resources per CLB are provided for
on-chip 3-state busses. Each 3-state buffer has access
alternately to two horizontal lines, which can be partitioned
as shown in Figure 28. The switch matrices corresponding
to SelectRAM memory and multiplier or I/O blocks are
skipped.
Number of 3-State Buffers
Table 11 shows the number of 3-state buffers available in
each Virtex-II device. The number of 3-state buffers is twice
the number of CLB elements.
Table 11: Virtex-II 3-State Buffers
Device
3-State Buffers Total Number
per Row
of 3-State Buffers
XC2V40
16
128
XC2V80
16
256
XC2V250
32
768
XC2V500
48
1,536
XC2V1000
64
2,560
XC2V1500
80
3,840
XC2V2000
96
5,376
XC2V3000
112
7,168
XC2V4000
144
11,520
XC2V6000
176
16,896
XC2V8000
208
23,296
3 - state lines
Switch
matrix
CLB-II
Programmable
connection
Switch
matrix
CLB-II
DS031_09_032700
Figure 28: 3-State Buffer Connection to Horizontal Lines
CLB/Slice Configurations
Table 12 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
implemented in one of the configurations listed. Table 13 shows the available resources in all CLBs.
Table 12: Logic Resources in One CLB
Slices
LUTs Flip-Flops MULT_ANDs
Arithmetic &
Carry-Chains
SOP
Chains
Distributed
SelectRAM
Shift
Registers
TBUF
4
8
8
8
2
2
128 bits
128 bits
2
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
20