DS031 Datasheet, PDF (9/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs:
Functional Description
DS031-2 (v3.5) November 5, 2007
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II™ I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in Figure 1.
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Switch
Matrix
IOB
PAD4
IOB
PAD3
IOB
PAD2
IOB
PAD1
Differential Pair
Differential Pair
DS031_30_101600
Figure 1: Virtex-II Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V_CCINT = 1.5V),
output driver supply voltage (V_CCO) is dependent on the I/O
standard (see Table 1 and Table 2). An auxiliary supply volt-
age (V_CCAUX = 3.3 V) is required, regardless of the I/O
standard used. For exact supply voltage absolute maximum
ratings, see DC Input and Output Levels in Module 3.
All of the user IOBs have fixed-clamp diodes to V_CCO and to
ground. As outputs, these IOBs are not compatible or com-
pliant with 5V I/O standards. As inputs, these IOBs are not
normally 5V tolerant, but can be used with 5V I/O standards
when external current-limiting resistors are used. For more
details, see the “5V Tolerant I/Os“ Tech Topic at www.xil-
inx.com.
Table 3 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 8.
Product Specification
Table 1: Supported Single-Ended I/O Standards
IOSTANDARD
Attribute
LVTTL
Output
V_CCO
3.3
Input
V_CCO
3.3
Input
V_REF
N/R ⁽³⁾
Board
Termination
Voltage (V_TT)
N/R
LVCMOS33
3.3
3.3
N/R
N/R
LVCMOS25
2.5
2.5
N/R
N/R
LVCMOS18
1.8
1.8
N/R
N/R
LVCMOS15
1.5
1.5
N/R
N/R
PCI33_3
3.3
3.3
N/R
N/R
PCI66_3
3.3
3.3
N/R
N/R
PCI-X
3.3
3.3
N/R
N/R
GTL
Note (1) Note (1) 0.8
1.2
GTLP
Note (1) Note (1) 1.0
1.5
HSTL_I
1.5
N/R
0.75
0.75
HSTL_II
1.5
N/R
0.75
0.75
HSTL_III
1.5
N/R
0.9
1.5
HSTL_IV
1.5
N/R
0.9
1.5
HSTL_I_18
1.8
N/R
0.9
0.9
HSTL_II_18
1.8
N/R
0.9
0.9
HSTL_III _18
1.8
N/R
1.1
1.8
HSTL_IV_18
1.8
N/R
1.1
1.8
SSTL18_I⁽²⁾
1.8
N/R
0.9
0.9
SSTL18_II
1.8
N/R
0.9
0.9
SSTL2_I
2.5
N/R
1.25
1.25
SSTL2_II
2.5
N/R
1.25
1.25
SSTL3_I
3.3
N/R
1.5
1.5
SSTL3_II
3.3
N/R
1.5
1.5
AGP-2X/AGP
3.3
N/R
1.32
N/R
Notes:
1. V_CCO of GTL or GTLP should not be lower than the termination
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V_CCO to 1.5V.
2. SSTL18_I is not a JEDEC-supported standard.
3. N/R = no requirement.
© 2000–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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