DS031 Datasheet, PDF (56/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 12: Register-to-Register Performance (Continued)
Description
Device Used & Speed
Grade
8-bit Adder
XC2V1000 -5
16-bit Adder
XC2V1000 -5
64-bit Adder
XC2V1000 -5
64-bit Counter
XC2V1000 -5
64-bit Accumulator
XC2V1000 -5
Multiplier 18x18 (with Block RAM inputs)
XC2V1000 -5
Multiplier 18x18 (with Register inputs)
XC2V1000 -5
Memory
Block RAM
Single-Port 4096 x 4 bits
Single-Port 2048 x 9 bits
Single-Port 1024 x 18 bits
Single-Port 512 x 36 bits
Dual-Port A:4096 x 4 bits & B:1024 x 18 bits
Dual-Port A:1024 x 18 bits & B:1024 x 18 bits
Dual-Port A:2048 x 9 bits & B: 512 x 36 bits
Distributed RAM
Single-Port 32 x 8-bit
XC2V1000 -5
Single-Port 64 x 8-bit
XC2V1000 -5
Single-Port 128 x 8-bit
XC2V1000 -5
Dual-Port 16 x 8
XC2V1000 -5
Dual-Port 32 x 8
XC2V1000 -5
Dual-Port 64 x 8
XC2V1000 -5
Shift Registers
128-bit SRL
256-bit SRL
FIFOs (Async. in Block RAM)
1024 x 18-bit Read
1024 x 18-bit Write
FIFOs (Sync. in SRL)
128 x 8-bit
128 x 16-bit
Register-to-Register
Performance
292
239
114
114
110
88
105
278
277
270
253
257
259
250
387
335
266
409
311
294
N/A
N/A
279
172
N/A
N/A
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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