DS031 Datasheet, PDF (126/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs: Pinout Information
FG676/FGG676 Fine-Pitch BGA Package
As shown in Table 8, XC2V1500, XC2V2000, and XC2V3000 Virtex-II devices are available in the FG676/FGG676 fine-pitch
BGA package. Pins in the XC2V1500, XC2V2000, and XC2V3000 devices are the same, except for the pin differences in the
XC2V1500 and XC2V2000 devices shown in the No Connect columns. Following this table are the FG676/FGG676
Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
Pin Number No Connect in XC2V1500
0
IO_L01N_0
D6
0
IO_L01P_0
C6
0
IO_L02N_0
B1
0
IO_L02P_0
A2
0
IO_L03N_0/VRP_0
D7
0
IO_L03P_0/VRN_0
C7
0
IO_L04N_0/VREF_0
B3
0
IO_L04P_0
A3
0
IO_L05N_0
G6
0
IO_L05P_0
G7
0
IO_L06N_0
E6
0
IO_L06P_0
E7
0
IO_L19N_0
B4
0
IO_L19P_0
A4
0
IO_L21N_0
B5
0
IO_L21P_0/VREF_0
A5
0
IO_L22N_0
B6
0
IO_L22P_0
A6
0
IO_L24N_0
A7
0
IO_L24P_0
A8
0
IO_L25N_0
E8
NC
0
IO_L25P_0
D8
NC
0
IO_L27N_0
G8
NC
0
IO_L27P_0/VREF_0
F8
NC
0
IO_L49N_0
C8
0
IO_L49P_0
B8
0
IO_L51N_0
D9
0
IO_L51P_0/VREF_0
E9
0
IO_L52N_0
F9
0
IO_L52P_0
G9
0
IO_L54N_0
B9
0
IO_L54P_0
A9
0
IO_L67N_0
C9
No Connect in XC2V2000
NC
NC
NC
NC
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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