DS031 Datasheet, PDF (82/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Global Clock Setup and Hold for LVTTL Standard, Without DCM
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Table 37: Global Clock Setup and Hold for LVTTL Standard, Without DCM
Speed Grade
Description
Symbol
Device
-6
-5
-4
Units
Input Setup and Hold Time Relative to
Global Clock Input Signal for LVTTL
Standard.⁽²⁾
For data input with different
standards, adjust the setup time delay
by the values shown in IOB Input
Switching Characteristics Standard
Adjustments, page 11.
Full Delay
Global Clock and IFF⁽¹⁾ without DCM
T_PSFD/T_PHFD
XC2V40 1.92/ 0.00 1.92/ 0.00
2.21/ 0.00
ns
XC2V80 2.10/ 0.00 2.10/ 0.00
2.21/ 0.00
ns
XC2V250 1.92/ 0.00 1.92/ 0.00
2.21/ 0.00
ns
XC2V500 1.92/ 0.00 1.92/ 0.00
2.21/ 0.00
ns
XC2V1000 1.92/ 0.00 1.92/ 0.00
2.21/ 0.00
ns
XC2V1500 1.92/ 0.00 1.92/ 0.00
2.21/ 0.00
ns
XC2V2000 1.92/ 0.00 1.92/ 0.00
2.21/ 0.00
ns
XC2V3000 1.92/ 0.00 1.92/ 0.00
2.21/ 0.00
ns
XC2V4000 2.00/ 0.00 2.00/ 0.00
2.30/ 0.00
ns
XC2V6000 1.92/ 0.50 1.92/ 0.50
2.21/ 0.50
ns
XC2V8000
2.38/ 0.00
2.60/ 0.00
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. These values are parametrically measured.
DS031-3 (v3.5) November 5, 2007
Product Specification
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