DS031 Datasheet, PDF (55/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Virtex-II Performance Characteristics
This section provides the performance characteristics of
some common functions and designs implemented in
Virtex-II devices. The numbers reported here are worst-case
values; they have all been fully characterized. Note that
these values are subject to the same guidelines as Virtex-II
Switching Characteristics, page 9 (speed files).
Table 11 provides pin-to-pin values (in nanoseconds)
including IOB delays; that is, delay through the device from
input pin to output pin. In the case of multiple inputs and out-
puts, the worst delay is reported.
Table 11: Pin-to-Pin Performance
Description
Device Used & Speed Grade Pin-to-Pin (with I/O delays) Units
Basic Functions
16-bit Address Decoder
XC2V1000 -5
6.3
ns
32-bit Address Decoder
XC2V1000 -5
7.7
ns
64-bit Address Decoder
XC2V1000 -5
9.3
ns
4:1 MUX
XC2V1000 -5
5.7
ns
8:1 MUX
XC2V1000 -5
6.5
ns
16:1 MUX
XC2V1000 -5
6.7
ns
32:1 MUX
XC2V1000 -5
8.7
ns
Combinatorial (pad to LUT to pad)
XC2V1000 -5
5.0
ns
Memory
Block RAM
Pad to setup
1.6
ns
Clock to Pad
9.5
ns
Distributed RAM
Pad to setup
XC2V1000 -5
2.7
ns
Clock to Pad
XC2V1000 -5
5.1 (no clk skew)
ns
Table 12 shows internal (register-to-register) performance. Values are reported in MHz.
Table 12: Register-to-Register Performance
Description
Device Used & Speed
Grade
Register-to-Register
Performance
Basic Functions
16-bit Address Decoder
XC2V1000 -5
398
32-bit Address Decoder
XC2V1000 -5
291
64-bit Address Decoder
XC2V1000 -5
274
4:1 MUX
XC2V1000 -5
563
8:1 MUX
XC2V1000 -5
454
16:1 MUX
XC2V1000 -5
414
32:1 MUX
XC2V1000 -5
323
Register to LUT to Register
XC2V1000 -5
613
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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