DS031 Datasheet, PDF (59/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
IOB Input Switching Characteristics Standard Adjustments
Table 15 gives all standard-specific data input delay adjustments.
Table 15: IOB Input Switching Characteristics Standard Adjustments
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
LVDSEXT (Extended Mode), 2.5V
LVDSEXT, 3.3V
ULVDS (Ultra LVDS), 2.5V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
SSTL, Class I, 3.3V
SSTL, Class II, 3.3V
AGP-2X/AGP (Accelerated Graphics Port)
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
LVDCI, 1.8V
LVDCI, 1.5V
IOSTANDARD
Attribute
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVDS_25
LVDS_33
LVDSEXT_25
LVDSEXT_33
ULVDS_25
BLVDS_25
LDT_25
LVPECL_33
PCI33_3
PCI66_3
PCIX
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III_18
HSTL_IV_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_ II
AGP
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
Timing
Parameter
T_ILVTTL
T_ILVCMOS33
T_ILVCMOS25
T_ILVCMOS18
T_ILVCMOS15
T_{ILVDS_25}
T_{ILVDS_33}
T_{ILVDSEXT_25}
T_{ILVDSEXT_33}
T_{IULVDS_25}
T_{IBLVDS_25}
T_{ILDT_25}
T_{ILVPECL_33}
T_{IPCI33_3}
T_{IPCI66_3}
T_IPCIX
T_IGTL
T_IGTLP
T_{IHSTL_I}
T_{IHSTL_II}
T_{IHSTL_III}
T_{IHSTL_IV}
T_{IHSTL_I_18}
T_{IHSTL_II_18}
T_{IHSTL_III_18}
T_{IHSTL_IV_18}
T_{ISSTL18_I}
T_{ISSTL18_II}
T_{ISSTL2_I}
T_{ISSTL2_II}
T_{ISSTL3_I}
T_{ISSTL3_II}
T_IAGP
T_{ILVDCI_33}
T_{ILVDCI_25}
T_{ILVDCI_18}
T_{ILVDCI_15}
Speed Grade
-6
-5
-4
0.00 0.00 0.00
0.00 0.00 0.00
0.11 0.11 0.12
0.42 0.43 0.49
0.98 1.00 1.15
0.60 0.60 0.69
0.60 0.60 0.69
0.68 0.69 0.79
0.56 0.56 0.65
0.48 0.49 0.56
0.68 0.69 0.79
0.48 0.49 0.56
0.60 0.60 0.69
0.00 0.00 0.00
0.00 0.00 0.00
0.00 0.00 0.00
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.35 0.35 0.40
0.35 0.35 0.40
0.35 0.35 0.40
0.00 0.00 0.00
0.11 0.11 0.12
0.42 0.43 0.49
0.98 1.00 1.14
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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