DS031 Datasheet, PDF (76/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Serial DIN
CCLK
Serial DOUT
1 T_DCC
2 T_CCD
4 T_CCH
5 T_CCL
3 T_CCO
Figure 3: Slave Serial Mode Timing Sequence
ds083-3_08_111104
CCLK
(Output)
Serial DIN
1 T_DSCK
2
T_CKDS
Serial DOUT
Figure 4: Master Serial Mode Timing Sequence
ds083-3_09_111104
.
Table 31: Master/Slave Serial Mode Timing Characteristics
Description
Figure
References
Symbol
Value
CCLK
DIN setup/hold, slave mode (Figure 3)
DIN setup/hold, master mode (Figure 4)
DOUT
High time
Low time
Maximum start-up frequency
Maximum frequency
Frequency tolerance, master mode with
respect to nominal
1/2
T_DCC/T_CCD
5.0/0.0
1/2
T_DSCK/T_CKDS
5.0/0.0
3
T_CCO
12.0
4
T_CCH
5.0
5
T_CCL
5.0
F_{CC_STARTUP}
F_{CC_SERIAL}
50
66 ⁽¹⁾
+45%
–30%
Notes:
1. If no provision is made in the design to adjust the frequency of CCLK, F_{CC_SERIAL} should not exceed F_{CC_STARTUP}.
Units
ns, min
ns, min
ns, max
ns, min
ns, min
MHz, max
MHz, max
Master/Slave SelectMAP Parameters
Figure 5 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
Virtex-II Pro Platform FPGA User Guide.
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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