DS031 Datasheet, PDF (38/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs: Functional Description
DCM
CLKIN
CLKFB
RST
DSSEN
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
PSINCDEC _CLKFX
PSEN
CLKFX180
PSCLK
LOCKED
STATUS[7:0]
clock signal
PSDONE
control signal
DS031_67_112900
Figure 45: Digital Clock Manager
The DCM can be configured to delay the completion of the
Virtex-II configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.
The DCM has the following general control signals:
• RST input pin: resets the entire DCM
• LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
• STATUS output pins (active High): shown in Table 21.
Table 21: DCM Status Pins
Status Pin
Function
0
Phase Shift Overflow
1
CLKIN Stopped
2
CLKFX Stopped
3
N/A
4
N/A
5
N/A
6
N/A
7
N/A
Clock De-Skew
The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line. Addi-
tional delay is introduced so that clock edges arrive at inter-
nal registers and block RAMs simultaneously with the clock
edges arriving at the input clock pad. Alternatively, external
clocks, which are also de-skewed relative to the input clock,
can be generated for board-level routing. All DCM output
clocks are phase-aligned to CLK0 and, therefore, are also
phase-aligned to the input clock.
To achieve clock de-skew, the CLKFB input must be con-
nected, and its source must be either CLK0 or CLK2X. Note
that CLKFB must always be connected, unless only the CLKFX
or CLKFX180 outputs are used and de-skew is not required.
Frequency Synthesis
The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with divi-
sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,
8, 9, 10, 11, 12, 13, 14, 15, and 16.
The CLKFX and CLKFX180 outputs can be used to pro-
duce clocks at the following frequency:
FREQ_CLKFX = (M/D) * FREQ_CLKIN
where M and D are two integers. Specifications for M and D
are provided under DCM Timing Parameters in Module 3.
By default, M=4 and D=1, which results in a clock output fre-
quency four times faster than the clock input frequency
(CLKIN).
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles (with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode).
Note that CLK2X and CLK2X180 are not available in
high-frequency mode.
Phase Shifting
The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
CLKIN and CLKFB is a specified fraction of the input clock
period.
In variable mode, the PHASE_SHIFT value can also be
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active. Figure 46 illustrates the effects of fine-phase
shifting. For more information on DCM features, see the
Virtex-II User Guide.
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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