DS031 Datasheet, PDF (3/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs: Introduction and Overview
Table 1: Virtex-II Field-Programmable Gate Array Family Members
CLB
(1 CLB = 4 slices = Max 128 bits)
Device
System Array
Gates Row x Col.
Slices
Maximum
Distributed
RAM Kbits
Multiplier
Blocks
XC2V40
40K
8x8
256
8
4
XC2V80
80K
16 x 8
512
16
8
XC2V250
250K
24 x 16
1,536
48
24
XC2V500
500K
32 x 24
3,072
96
32
XC2V1000
1M
40 x 32 5,120
160
40
XC2V1500 1.5M
48 x 40
7,680
240
48
XC2V2000
2M
56 x 48 10,752
336
56
XC2V3000
3M
64 x 56 14,336
448
96
XC2V4000
4M
80 x 72 23,040
720
120
XC2V6000
6M
96 x 88 33,792
1,056
144
XC2V8000
8M 112 x 104 46,592
1,456
168
Notes:
1. See details in Table 2, “Maximum Number of User I/O Pads”.
SelectRAM Blocks
18 Kbit
Blocks
4
8
24
32
40
48
56
96
120
144
168
Max RAM
(Kbits)
72
144
432
576
720
864
1,008
1,728
2,160
2,592
3,024
Max I/O
DCMs Pads⁽¹⁾
4
88
4
120
8
200
8
264
8
432
8
528
8
624
12
720
12
912
12
1,104
12
1,108
General Description
The Virtex-II family is a platform FPGA developed for high
performance from low-density to high-density designs that
are based on IP cores and customized modules. The family
delivers complete solutions for telecommunication, wire-
less, networking, video, and DSP applications, including
PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal
process and the Virtex-II architecture are optimized for high
speed with low power consumption. Combining a wide vari-
ety of flexible features and a large range of densities up to
10 million system gates, the Virtex-II family enhances pro-
grammable logic design capabilities and is a powerful alter-
native to mask-programmed gates arrays. As shown in
Table 1, the Virtex-II family comprises 11 members, ranging
from 40K to 8M system gates.
Packaging
Offerings include ball grid array (BGA) packages with
0.80 mm, 1.00 mm, and 1.27 mm pitches. In addition to tra-
ditional wire-bond interconnects, flip-chip interconnect is
used in some of the BGA offerings. The use of flip-chip
interconnect offers more I/Os than is possible in wire-bond
versions of the similar packages. Flip-chip construction
offers the combination of high pin count with high thermal
capacity.
Wire-bond packages CS, FG, and BG are optionally avail-
abe in Pb-free versions CSG, FGG, and BGG. See Virtex-II
Ordering Examples, page 6.
Table 2 shows the maximum number of user I/Os available.
The Virtex-II device/package combination table (Table 6 at
the end of this section) details the maximum number of I/Os
for each device and package using wire-bond or flip-chip
technology.
Table 2: Maximum Number of User I/O Pads
Device
Wire-Bond
Flip-Chip
XC2V40
88
-
XC2V80
120
-
XC2V250
200
-
XC2V500
264
-
XC2V1000
328
432
XC2V1500
392
528
XC2V2000
-
624
XC2V3000
516
720
XC2V4000
-
912
XC2V6000
-
1,104
XC2V8000
-
1,108
DS031-1 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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