DS031 Datasheet, PDF (60/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
Description
IOSTANDARD
Attribute
Timing
Parameter
LVDCI, 3.3V, Half-Impedance
LVDCI_DV2_33
T_{ILVDCI_DV2_33}
LVDCI, 2.5V, Half-Impedance
LVDCI_DV2_25
T_{ILVDCI_DV2_25}
LVDCI, 1.8V, Half-Impedance
LVDCI_DV2_18
T_{ILVDCI_DV2_18}
LVDCI, 1.5V, Half-Impedance
LVDCI_DV2_15
T_{ILVDCI_DV2_15}
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI_15
T_{IHSLVDCI_15}
HSLVDCI, 1.8V
HSLVDCI_18
T_{IHSLVDCI_18}
HSLVDCI, 2.5V
HSLVDCI_25
T_{IHSLVDCI_25}
HSLVDCI, 3.3V
HSLVDCI_33
T_{IHSLVDCI_33}
GTL (Gunning Transceiver Logic) with DCI
GTL_DCI
T_{IGTL_DCI}
GTL Plus with DCI
GTLP_DCI
T_{IGTLP_DCI}
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL_I_DCI
T_{IHSTL_I_DCI}
HSTL, Class II, with DCI
HSTL_II_DCI
T_{IHSTL_II_DCI}
HSTL, Class III, with DCI
HSTL_III_DCI
T_{IHSTL_III_DCI}
HSTL, Class IV, with DCI
HSTL_IV_DCI
T_{IHSTL_IV_DCI}
HSTL, Class I, 1.8V, with DCI
HSTL_I_DCI_18
T_{IHSTL_I_DCI_18}
HSTL, Class II, 1.8V, with DCI
HSTL_II_DCI_18
T_{IHSTL_II_DCI_18}
HSTL, Class III, 1.8V, with DCI
HSTL_III_DCI_18 T_{IHSTL_III_DCI_18}
HSTL, Class IV, 1.8V, with DCI
HSTL_IV_DCI_18 T_{IHSTL_IV_DCI_18}
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL18_I_DCI
T_{ISSTL18_I_DCI}
SSTL, Class II, 1.8V, with DCI
SSTL18_II_DCI
T_{ISSTL18_II_DCI}
SSTL, Class I, 2.5V, with DCI
SSTL2_I_DCI
T_{ISSTL2_I_DCI}
SSTL, Class II, 2.5V, with DCI
SSTL2_II_DCI
T_{ISSTL2_II_DCI}
SSTL, Class I, 3.3V, with DCI
SSTL3_I_DCI
T_{ISSTL3_I_DCI}
SSTL, Class II, 3.3V, with DCI
SSTL3_II_DCI
T_{ISSTL3_II_DCI}
LVDS (Low-Voltage Differential Signaling), 2.5V, with DCI
LVDS_25_DCI
T_{ILVDS_25_DCI}
LVDS, 3.3V, with DCI
LVDS_33_DCI
T_{ILVDS_33_DCI}
LVDSEXT (LVDS Extended Mode), 2.5V, with DCI
LVDSEXT_25_DCI T_{ILVDSEXT_25_DCI}
LVDSEXT, 3.3V, with DCI
LVDSEXT_33_DCI T_{ILVDSEXT_33_DCI}
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see Table 18.
Speed Grade
-6
-5
-4
0.00 0.00 0.00
0.11 0.11 0.12
0.42 0.43 0.49
0.98 1.00 1.14
0.42 0.42 0.48
0.52 0.53 0.60
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.42 0.42 0.48
0.35 0.35 0.40
0.35 0.35 0.40
0.60 0.60 0.69
0.60 0.60 0.69
0.58 0.59 0.79
0.56 0.56 0.65
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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