DS031 Datasheet, PDF (68/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Clock Distribution Switching Characteristics
Table 20: Clock Distribution Switching Characteristics
Description
Global Clock Buffer I input to O output
Global Clock Buffer S input Setup/Hold
to I1 an I2 inputs
Symbol
T_GIO
T_GSI/T_GIS
Speed Grade
-6
-5
-4
0.47
0.52
0.59
0.55/ 0
0.61/ 0
0.70/ 0
Units
ns, Max
ns, Max
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see Figure 16 in Module 2). The values listed below
are worst-case. Precise values are provided by the timing analyzer.
Table 21: CLB Switching Characteristics
Speed Grade
Description
Symbol
-6
-5
-4
Units
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
Incremental delay routing through transparent latch to
XQ/YQ outputs
Sequential Delays
T_ILO
T_IF5
T_IF5X
T_IFXY
T_INAFX
T_INBFX
T_SOPSOP
T_IFNCTL
0.35
0.39
0.44
ns, Max
0.57
0.63
0.72
ns, Max
0.76
0.83
0.95
ns, Max
0.36
0.39
0.45
ns, Max
0.26
0.28
0.32
ns, Max
0.26
0.28
0.32
ns, Max
0.35
0.38
0.44
ns, Max
0.41
0.45
0.51
ns, Max
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times Before/After Clock CLK
BX/BY inputs
DY inputs
DX inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
T_CKO
T_CKLO
T_DICK/T_CKDI
T_DYCK/T_CKDY
T_DXCK/T_CKDX
T_CECK/T_CKCE
T_SRCK/T_SCKR
0.45
0.50
0.57
ns, Max
0.54
0.59
0.68
ns, Max
0.30/–0.07
0.30/–0.07
0.30/–0.07
0.19/–0.06
0.21/–0.02
0.33/–0.08
0.33/–0.08
0.33/–0.08
0.21/–0.07
0.23/–0.03
0.37/–0.09
0.37/–0.09
0.37/–0.09
0.24/–0.08
0.26/–0.03
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
Minimum Pulse Width, SR/BY inputs (asynchronous)
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Toggle Frequency (MHz) (for export control)
T_CH
T_CL
T_RPW
T_RQ
F_TOG
0.61
0.67
0.77
ns, Min
0.61
0.67
0.77
ns, Min
0.61
0.67
0.77
ns, Min
1.06
1.17
1.34
ns, Max
820
750
650
MHz
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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