DS031 Datasheet, PDF (127/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Pinout Information
Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
Pin Number No Connect in XC2V1500
0
IO_L67P_0
C10
0
IO_L69N_0
F10
0
IO_L69P_0/VREF_0
G10
0
IO_L70N_0
E10
0
IO_L70P_0
D10
0
IO_L72N_0
A10
0
IO_L72P_0
A11
0
IO_L73N_0
F11
NC
0
IO_L73P_0
E11
NC
0
IO_L75N_0
G11
NC
0
IO_L75P_0/VREF_0
H11
NC
0
IO_L76N_0
D11
NC
0
IO_L76P_0
C11
NC
0
IO_L78N_0
B11
NC
0
IO_L78P_0
B12
NC
0
IO_L91N_0/VREF_0
G12
0
IO_L91P_0
H12
0
IO_L92N_0
F12
0
IO_L92P_0
E12
0
IO_L93N_0
D12
0
IO_L93P_0
C12
0
IO_L94N_0/VREF_0
G13
0
IO_L94P_0
H13
0
IO_L95N_0/GCLK7P
F13
0
IO_L95P_0/GCLK6S
E13
0
IO_L96N_0/GCLK5P
D13
0
IO_L96P_0/GCLK4S
C13
No Connect in XC2V2000
1
IO_L96N_1/GCLK3P
H14
1
IO_L96P_1/GCLK2S
H15
1
IO_L95N_1/GCLK1P
G14
1
IO_L95P_1/GCLK0S
F14
1
IO_L94N_1
E14
1
IO_L94P_1/VREF_1
D14
1
IO_L93N_1
A12
1
IO_L93P_1
A13
1
IO_L92N_1
A14
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
35