DS031 Datasheet, PDF (29/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs: Functional Description
Table 13: Virtex-II Logic Resources Available in All CLBs
Device
CLB Array: Number Number Max Distributed
Row x
of
of
SelectRAM or Shift
Column Slices LUTs
Register (bits)
Number
Number
Number
of
of
of SOP
Flip-Flops Carry-Chains⁽¹⁾ Chains⁽¹⁾
XC2V40
8x8
256
512
8,192
512
16
16
XC2V80
16 x 8
512
1,024
16,384
1,024
16
32
XC2V250
24 x 16
1,536 3,072
49,152
3,072
32
48
XC2V500
32 x 24
3,072 6,144
98,304
6,144
48
64
XC2V1000
40 x 32
5,120 10,240
163,840
10,240
64
80
XC2V1500
48 x 40
7,680 15,360
245,760
15,360
80
96
XC2V2000
56 x 48
10,752 21,504
344,064
21,504
96
112
XC2V3000
64 x 56
14,336 28,672
458,752
28,672
112
128
XC2V4000
80 x 72
23,040 46,080
737,280
46,080
144
160
XC2V6000
96 x 88
33,792 67,584
1,081,344
67,584
176
192
XC2V8000 112 x 104 46,592 93,184
1,490,944
93,184
208
224
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
18 Kbit Block SelectRAM Resources
Introduction
Virtex-II devices incorporate large amounts of 18 Kbit block
SelectRAM. These complement the distributed SelectRAM
resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II block SelectRAM is an 18
Kbit true dual-port RAM with two independently clocked and
independently controlled synchronous ports that access a
common storage area. Both ports are functionally identical.
CLK, EN, WE, and SSR polarities are defined through con-
figuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II block SelectRAM supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in Table 14.
Table 14: Dual- and Single-Port Configurations
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kbit memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kbit
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as 8 +
1, 16 + 2, or 32 + 4. These extra parity bits are stored and
behave exactly as the other bits, including the timing param-
eters. Video applications can use the 9-bit ratio of Virtex-II
block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory
as illustrated in Figure 29. Input data bus and output data
bus widths are identical.
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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