DS031 Datasheet, PDF (146/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Pinout Information
BG575/BGG575 Standard BGA Package
As shown in Table 9, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the BG575/BGG575 BGA
package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in the
XC2V1000 and XC2V1500 devices shown in the No Connect columns. Following this table are the BG575/BGG575
Standard BGA Package Specifications (1.27mm pitch).
Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000
Bank
Pin Description
Pin Number No Connect in XC2V1000
0
IO_L01N_0
A3
0
IO_L01P_0
A4
0
IO_L02N_0
D5
0
IO_L02P_0
C5
0
IO_L03N_0/VRP_0
E6
0
IO_L03P_0/VRN_0
D6
0
IO_L04N_0/VREF_0
F7
0
IO_L04P_0
E7
0
IO_L05N_0
G8
0
IO_L05P_0
H9
0
IO_L06N_0
A5
0
IO_L06P_0
A6
0
IO_L19N_0
B5
0
IO_L19P_0
B6
0
IO_L21N_0
D7
0
IO_L21P_0/VREF_0
C7
0
IO_L22N_0
F8
0
IO_L22P_0
E8
0
IO_L24N_0
G9
0
IO_L24P_0
F9
0
IO_L49N_0
G10
0
IO_L49P_0
H10
0
IO_L51N_0
B7
0
IO_L51P_0/VREF_0
B8
0
IO_L52N_0
D8
0
IO_L52P_0
C8
0
IO_L54N_0
E9
0
IO_L54P_0
D9
0
IO_L67N_0
A8
NC
0
IO_L67P_0
A9
NC
0
IO_L69N_0
C9
NC
No Connect in XC2V1500
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
54