DS031 Datasheet, PDF (47/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
Date
07/16/02
09/26/02
12/06/02
05/07/03
06/19/03
08/01/03
10/14/03
03/29/04
06/24/04
03/01/05
11/05/07
Version
2.0
2.1
2.1.1
2.1.2
2.2
3.0
3.1
3.2
3.3
3.4
3.5
Revision
• Updated compatible input standards listed in Table 6.
• Changed number of resources available to the XC2V40 device in Table 13.
• Clarified Power On Reset information under Configuration Sequence.
• Cosmetic edits.
• Added qualification note to Figure 13, page 11.
• Corrected sentence in section Input/Output Individual Options, page 4, to read “The
optional weak-keeper circuit is connected to each user I/O pad.”
• Corrected typographical errors in Table 3 for names of HSTL_[x]_DCI_18 standards.
• Removed Compatible Output Standards and Compatible Input Standards tables.
• Added new Table 5, Summary of Voltage Supply Requirements for All Input and
Output Standards. This table replaces deleted I/O standards tables.
• Added section Rules for Combining I/O Standards in the Same Bank, page 6.
All Virtex-II devices and speed grades now Production. See Table 13, Module 3.
• Added section Local Clocking, page 29.
• Table 1, page 1:
- Added SSTL18_I and SSTL18_II.
- Corrected names of 1.8V HSTL_I-IV standards to “HSTL_I-IV_18”.
- Corrected Input V_REF for HSTL_III-IV_18 from 1.08V to 1.1V.
- Changed “N/A” to “N/R” (no requirement).
• Table 2, page 2:
- Changed “N/A” to “N/R” (no requirement).
• Table 3, page 2:
- Added SSTL18_I_DCI, SSTL18_II_DCI, LVDS_33_DCI, LVDSEXT_33_DCI,
LVDS_25_DCI, and LVDSEXT_25_DCI.
- Corrected Input V_REF for HSTL_III-IV_18 from 1.08V to 1.1V.
• Sections Slave-Serial Mode and Master-Serial Mode, page 36: Changed "rising" to
"falling" edge with respect to DOUT.
• Added verbiage to section Bitstream Encryption, page 38: “For devices that support
this feature, please contact your sales representative for specific ordering part
number.”
• Table 2, page 2, and Table 5, page 7: Removed LVDS_33_DCI and
LVDSEXT_33_DCI from tables.
• Table 26, page 37: Updated bitstream lengths.
• Section BUFGMUX, page 29: Corrected the definition of the "presently selected clock"
to be I0 or I1. Corrected signal names in Figure 44 and associated text from CLK0 and
CLK1 to I0 and I1.
• Recompiled for backward compatibility with Acrobat 4 and above.
• Table 1, page 1: Added example to Footnote (1) regarding V_CCO rules for GTL and
GTLP.
• Added reference to Pb-free package types in Figure 7, page 6.
• Reassigned heading hierarchies for better agreement with content.
• Table 2: Corrected V_OD output voltages.
• Table 26: Updated bitstream lengths.
• Updated copyright statement and legal disclaimer.
• Boundary-Scan (JTAG, IEEE 1532) Mode, page 37: Updated IEEE 1149.1 compliance
statement.
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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