DS031 Datasheet, PDF (85/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Output Clock Jitter
Table 40: Output Clock Jitter
Description
Symbol
Clock Synthesis Period Jitter
CLK0
CLKOUT_PER_JITT_0
CLK90
CLKOUT_PER_JITT_90
CLK180
CLKOUT_PER_JITT_180
CLK270
CLKOUT_PER_JITT_270
CLK2X, CLK2X180
CLKOUT_PER_JITT_2X
CLKDV (integer division)
CLKOUT_PER_JITT_DV1
CLKDV (non-integer division)
CLKOUT_PER_JITT_DV2
CLKFX, CLKFX180
CLKOUT_PER_JITT_FX
Notes:
1. Values for this parameter are available at www.xilinx.com.
Constraints
Speed Grade
-6
-5
-4
Units
±100 ±100 ±100
ps
±150 ±150 ±150
ps
±150 ±150 ±150
ps
±150 ±150 ±150
ps
±200 ±200 ±200
ps
±150 ±150 ±150
ps
±300 ±300 ±300
ps
Note 1 Note 1 Note 1 ps
Output Clock Phase Alignment
Table 41: Output Clock Phase Alignment
Speed Grade
Description
Symbol
Constraints
-6
-5
-4
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
CLKIN_CLKFB_PHASE
±50
±50
±50
Phase Offset Between Any DCM Outputs
All CLK outputs
CLKOUT_PHASE
±140 ±140 ±140
Duty Cycle Precision
DLL outputs⁽¹⁾
CLKOUT_DUTY_CYCLE_DLL⁽²⁾
±150 ±150 ±150
CLKFX outputs
CLKOUT_DUTY_CYCLE_FX
±100 ±100 ±100
Notes:
1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE.
3. Specification also applies to PSCLK.
Units
ps
ps
ps
ps
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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